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Espressif Systems /ESP32-S3 /SPI1 /FLASH_SUS_CMD

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Interpret as FLASH_SUS_CMD

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (FLASH_PER)FLASH_PER 0 (FLASH_PES)FLASH_PES 0 (FLASH_PER_WAIT_EN)FLASH_PER_WAIT_EN 0 (FLASH_PES_WAIT_EN)FLASH_PES_WAIT_EN 0 (PES_PER_EN)PES_PER_EN 0 (PESR_IDLE_EN)PESR_IDLE_EN

Description

SPI1 flash suspend control register

Fields

FLASH_PER

program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
FLASH_PES

program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
FLASH_PER_WAIT_EN

Set this bit to add delay time after program erase resume(PER) is sent.
FLASH_PES_WAIT_EN

Set this bit to add delay time after program erase suspend(PES) command is sent.
PES_PER_EN

Set this bit to enable PES transfer trigger PES transfer option.
PESR_IDLE_EN

1: Separate PER flash wait idle and PES flash wait idle. 0: Not separate.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data